1. Field
The present disclosure relates generally to semiconductor devices with vertical channels and methods of making them.
2. Background Art
In a conventional silicon transistor that includes a source, a gate, and a drain, channel length (LG) is the length between the source to the drain inside a silicon substrate. This channel length is limited by lithography capabilities. In conventional methods, the channel length can be no smaller than 28 nm or 20 nm. The channel length of 20 nm can be achieved using double or multiple patterning, which is expensive as multiple patterning increases the processing cost. As the need for smaller semiconductors increases, there is a need to make the channel length even smaller than 20 nm. As the channel length gets smaller, the gate voltage also gets reduced. However, because of gate capacitance coupling, the gate voltage cannot be scaled as the channel length gets scaled. In other words, one benefit of smaller channel length is that a smaller gate voltage can be applied. However, this gate voltage cannot get smaller than a limit that is forced by gate capacitive coupling in a conventional lateral transistor. Also, smaller channel lengths can result in increased source/drain leakage in the off state. Further, a small channel length can cause drain-induced barrier lowering (DIBL) effect that can result in premature turning on of the transistor when a high drain voltage is applied. Additionally, there are multiple manufacturing challenges with conventional methods for making the channel length smaller, these manufacturing challenges include channel doping uniformity, line edge roughness, and high cost of multiple patterning requirements.
Current projection lithography printing technology can limit channel length. In addition, contacted poly pitch (CPP) less than 78 nm will require multiple patterning for resolution and manufacturability. Also, Extreme Ultra Violate (EUV) can print small channel lengths, however, current throughput is prohibitively slow and high cost, making EUV is undesirable.
Three dimensional (3D) transistors have been developed in an attempt for smaller channel length. For example, FinFET transistors have thin silicon “fins”, where each fin includes a double gate region wrapped around the conducting channels. FinFETs have been manufactured with channel lengths of 16 nm or 14 nm. However, these 3D transistors have limitations similar to the conventional 2D (e.g., planar) transistors, such as: the channel length being limited by lithography capability, the gate length being coupled with device pitch, negative effects of gate capacitive coupling, off-state source/drain leakage, DIBL effects, etc. Further, manufacturing 3D transistors is more expensive than 2D transistors. Also, because the fins are pre-manufactured, the gate width in 3D transistors can only be a function of the width of the pre-manufactured fins and not easily changed. Further, because of the 3D structure, the coupling capacity is higher and manufacturing is more challenging as yield problems arise due to stress control and uniformity of the 3D structure.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, generally, like reference numbers indicate identical or functionally similar elements. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.